Difficult-to-manufacture patterns within semiconductor design layouts include those which generate design rule check errors, lithography printability errors, double patterning technology-compliance check errors, design for manufacturability (DFM) rule check errors, etc. Existing solutions for resolving difficult-to-manufacture patterns generally fall into two categories: hand-drawn fixes and automated rule-based fixes.
Hand-drawn fixes are manual fixes that are made by a layout designer using a computer-aided design (CAD) tool. Guidance on fixing difficult-to-manufacture patterns is provided in the form of error markers with annotations generated by a rule-checking engine. Layout designers must iteratively modify the designs until all checks are passed. Consequently, hand-drawn fixes lack consistency as they rely on a human operator or designer to correct identical errors in the same exact manner, thus inducing variability in the final manufactured product.
Automated rule-based fixes are created by a manipulation engine that, through a group of coded rules, identifies the difficult-to-manufacture geometries and generates new geometries to replace them. The coded rules search for features based on a sequence of polygonal or edge based measurement commands. Consequently, each additional dimensional constraint or measurement incurs additional computation time and complexity. Comprehensive, rule-based scripts are required for automated rule-based fixes, which can be difficult to code, particularly for complex layout patterns. A pattern with N edges may be represented by N*(N−1) edge-pair constraints. Thus, it is impractical to implement approximately N*(N−1) coded rules per pattern.
A pattern-based methodology is an effective alternative to both of the above solutions when used to identify complex, difficult-to-manufacture layout patterns, such as those which cause lithography hotspots. However, once a hotspot is identified through pattern matching, fixing the layout still requires manual effort.
A need therefore exists for a methodology allowing for automated context-aware pattern-based semiconductor design layout correction.